This invention relates generally to semiconductor devices, and more particular the invention relates to field effect devices fabricated in silicon-on-insulator structures.
Silicon-on-insulator (SO) technology employs a layer of semiconductor material overlying an insulation layer on a supporting bulk wafer. The structure can be formed by a number of well-known techniques, such as zone melting and recrystallization (ZMR) separation by implanted oxygen (SIMOX) or Bonded and Etchback (BESOI). Typically, the structure comprises a film of monocrystalline silicon on a buried layer of silicon oxide in a monocrystalline silicon substrate.
Field effect transistors such as MOSFETs fabricated in the silicon film of an SOI structure have many advantages over MOSFETs fabricated on the traditional bulk silicon substrates including resistance to short-channel effect, steeper subthreshold slopes, increased current drive, higher packing density, reduced parasitic capacitance, and simpler processing steps. In the past, the range of SOI applications has been limited due to high cost and inferior crystalline quality of SOI wafers. However, recent advancements in the SOI silicon film quality, buried oxide quality, and manufacturing throughput have opened the door to a multitude of ultra large scale integration (ULSI) applications. Combined with the continually increasing cost of bulk silicon submicron integrated circuit processes and the lower complexity/cost of SOI integrated circuit processes, SOI technology shows great potential to become the low cost mainstream production technology.
Despite all of the attractiveness of SOI technology, there are obstacles which cancel part of the benefit of using SOI for high-performance, high-density ULSI circuits. The problem is especially severe for analog circuits or mixed-mode circuits, which contain both analog and digital circuits.
MOSFETs fabricated with SOI technology include non-fully depleted MOSFETs with silicon film thickness greater than the maximum channel depletion width and fully-depleted MOSFETs having silicon film thickness less than the maximum channel depletion width. Unlike bulk silicon MOSFETs, the substrate of an SOI MOSFET is usually electrically floating. In a non-fully depleted MOSFET, carriers (holes in nMOSFETs and electrons in pMOSFETs) generated by impact ionization accumulate near the source/body junction of the MOS transistor, and eventually sufficient carriers will accumulate to forward bias the body with respect to the source thus lowering the threshold voltage through the body-bias effect. Extra current will start flowing resulting in a "kink" in the I-V characteristics as shown in FIG. 1. This reduces the achievable gain and dynamic swing in analog circuits, and gives rise to abnormality in the transfer characteristics in digital circuits.
In a fully-depleted SOI MOSFET, the channel is depleted completely under normal operations. The source/channel junction has a lower potential barrier, and the carriers generated by impact ionization have smaller effect on the body and channel potential, thus the "kink" softens. But the resulting output resistance as illustrated in FIG. 2 is poor, thus making SOI technology less attractive than conventional bulk technology in analog circuits.
Furthermore, in fully-depleted MOSFETs, the depletion charge is reduced for a given body doping concentration, leading to a smaller threshold voltage. Threshold voltage becomes very sensitive to variations in the silicon film thickness, which makes the fabrication of high performance circuits very difficult. Additionally, the reduction of silicon film thickness in a fully-depleted MOSFET gives rise to high source/drain series resistance which in turn lowers the device operation speed. Silicidation can help improve the series resistance, but it will create mechanical stress and the process is hard to control on thin film silicon. One solution to the series resistance problem is to selectively reduce the silicon film thickness over the channel region. However, the resulting recessed region and the polysilicon gate are not automatically aligned. To allow for the possible misalignment, the recessed thin silicon region must be made longer than the gate. This reduces the device performance and density, and results in asymmetrical devices.
Another problem common to both fully-depleted and non-fully-depleted SOI MOSFETs is the parasitic floating-base lateral bipolar transistor existing in parallel with SOI MOSFETs. Band-to-band tunneling generated (GIDL) drain leakage and drain/body junction leakage due to thermal generation are multiplied by the gain of the parasitic bipolar junction transistor, which might be as high as 100. Low breakdown voltage and anomalously steep subthreshold slope due to a decreasing threshold voltage has been observed.
Problems due to the floating body can be solved by providing a contact to the body for hole current collection. However, the currently available hole collection schemes, including the use of a side-contact or the use of a mosaic source are very inefficient and consume significant amounts of device area. A dual source structure has been proposed which depends on an aluminum spiking phenomenon to make contact to the P region, which is sensitive to process variations. Further, the structure is not compatible with VLSI junction and contact technology such as silicidation.
Another major obstacle to the use of SOI technology in production is electrostatic discharge (ESD) susceptibility. In bulk-substrate technology, good ESD protection levels have been demonstrated by using nMOS/CMOS buffers. However, this protection scheme is not compatible with SOI structures. For example, thick-field-oxide devices are not available on an SOI substrate. Large-area low-series-resistance (vertical) PN junctions are not available as the silicon film can be thinner than 100 nm. Experimental results demonstrate that ESD performance on SOI wafers are much worse than bulk technology. This can be due to two reasons, namely the poor thermal conductivity of the buried oxide enhances the failure due to Joule heating, and the reduction of silicon film thickness and junction depth increases the ESD current density. Severe localized silicon heating can result, which causes junction melting and polysilicon melt filaments to form, which cause electrical shorts among the gate, source, drain and body of the transistors and result in device failure. ESD protection schemes designed for SOI circuits have been proposed using additional circuits constructed with diodes and polysilicon resistors, however these devices consume large silicon area, introduce large delays, and are far from adequate.
The present invention is directed to providing SOI transistors which overcome or reduce the above problems.